CPC G06F 12/0246 (2013.01) [G06F 11/3037 (2013.01); G06F 12/0292 (2013.01); G11C 16/349 (2013.01); G06F 2212/7211 (2013.01)] | 20 Claims |
1. A system comprising:
a plurality of memory components, each memory component comprising a plurality of management groups, each management group including a plurality of sub-groups; and
a processing device, operatively coupled with the plurality of memory components to perform wear-leveling operations, the wear-leveling operations comprising:
maintaining a life write counter (LWC) for each of the management groups of the memory component, each LWC having a most-significant-bits (MSB) portion and a least-significant-bits (LSB) portion, a single shared LWC base representing the MSB portion of the LWCs of all of the management groups of the memory component, and separate, management-group-specific LWC offsets represent the LSB portions of the LWCs of the management groups of the memory component; and
determining, in connection with a first write operation to a first sub-group of a first management group of the memory component, to move user data from the first management group to a second management group of the memory component, and in response:
moving the user data from the first management group to the second management group of the memory component; and
incrementing a first LWC for the first management group.
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