US 11,789,836 B2
Debug for multi-threaded processing
Niraj Nandan, Plano, TX (US); Hetul Sanghvi, Murphy, TX (US); Mihir Mody, Bangalore (IN); Gary Cooper, Oakmont, PA (US); and Anthony Lell, San Antonio, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 31, 2021, as Appl. No. 17/462,046.
Application 17/462,046 is a continuation of application No. 16/236,745, filed on Dec. 31, 2018, granted, now 11,144,417.
Prior Publication US 2021/0397528 A1, Dec. 23, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/273 (2006.01); G06F 11/22 (2006.01); G06F 9/48 (2006.01); G06F 13/28 (2006.01); G06F 13/16 (2006.01)
CPC G06F 11/2733 (2013.01) [G06F 9/4843 (2013.01); G06F 11/2242 (2013.01); G06F 13/1668 (2013.01); G06F 13/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of hardware schedulers, different ones of the hardware schedulers configured to schedule different ones of a plurality of pipelines for processing instructions;
a debug control coupled to the hardware schedulers, and the debug control configured to control at least a controlled one of the hardware schedulers to halt, step, or resume a respective one of the pipelines corresponding to the controlled hardware scheduler to enable debugging of the pipeline independently of hardware schedulers other than the controlled hardware scheduler and independently of pipelines other than the respective pipeline; and
a hardware accelerator coupled to the controlled hardware scheduler and configured to execute instructions for the respective pipeline.