CPC G06F 11/2733 (2013.01) [G06F 9/4843 (2013.01); G06F 11/2242 (2013.01); G06F 13/1668 (2013.01); G06F 13/28 (2013.01)] | 20 Claims |
1. A system comprising:
a plurality of hardware schedulers, different ones of the hardware schedulers configured to schedule different ones of a plurality of pipelines for processing instructions;
a debug control coupled to the hardware schedulers, and the debug control configured to control at least a controlled one of the hardware schedulers to halt, step, or resume a respective one of the pipelines corresponding to the controlled hardware scheduler to enable debugging of the pipeline independently of hardware schedulers other than the controlled hardware scheduler and independently of pipelines other than the respective pipeline; and
a hardware accelerator coupled to the controlled hardware scheduler and configured to execute instructions for the respective pipeline.
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