US 11,789,819 B1
Seamless recovery of a hardware-based I/O path in a multi-function NVMe SSD
Horia C. Simionescu, Foster City, CA (US); Ramkumar Venkatachalam, Bengaluru (IN); and Anirban Kundu, Bengaluru (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 29, 2022, as Appl. No. 17/733,519.
Int. Cl. G06F 11/14 (2006.01); G11C 29/08 (2006.01)
CPC G06F 11/1415 (2013.01) [G11C 29/08 (2013.01); G06F 2201/82 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving signaling indicative of performance of a reset operation involving a first physical function associated with a controller of a memory device;
initiating a first timer that corresponds to an amount of time available for the first physical function associated with the controller of the memory device to complete execution of pending commands;
initiating a second timer that corresponds to an amount of time available for a second physical function associated with the controller of the memory device to complete execution of pending commands; and
initiating a third timer that corresponds to an amount of time available for the second physical function associated with the controller of the memory device to join a recovery operation that is instigated as a result of performance of the reset operation.