US 11,789,818 B2
Coordinated error correction
Scott E. Schaefer, Boise, ID (US); and Aaron P. Boehm, Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 9, 2022, as Appl. No. 17/690,772.
Application 17/690,772 is a continuation of application No. 16/940,783, filed on Jul. 28, 2020, granted, now 11,294,766.
Claims priority of provisional application 62/885,925, filed on Aug. 13, 2019.
Prior Publication US 2022/0197745 A1, Jun. 23, 2022
Int. Cl. G06F 11/10 (2006.01); H03M 13/29 (2006.01)
CPC G06F 11/1076 (2013.01) [H03M 13/2906 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, at a memory device, a read command from a host device;
reading, in response to the read command from a memory array of the memory device, a set of data and a first error correction code associated with the set of data;
generating, at the memory device based at least in part on reading the set of data and the first error correction code, a second error correction code for the set of data;
comparing, based at least in part on generating the second error correction code, the first error correction code and the second error correction code; and
transmitting, to the host device, the set of data and an indication of whether the first error correction code and the second error correction code match based at least in part on the comparing, wherein the indication also indicates whether an attempt to correct an error in the set of data was performed.