US 11,789,811 B2
Techniques for storing data to enhance recovery and detection of data corruption errors
Peter Mills, Santa Clara, CA (US); Michael Sullivan, Santa Clara, CA (US); Nirmal Saxena, Santa Clara, CA (US); and John Brooks, Santa Clara, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by Nvidia Corporation, Santa Clara, CA (US)
Filed on May 17, 2022, as Appl. No. 17/746,627.
Application 17/746,627 is a continuation of application No. 16/355,309, filed on Mar. 15, 2019, granted, now 11,474,897.
Prior Publication US 2022/0276924 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/10 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method, comprising:
swizzling a first plurality of data units to generate a first plurality of swizzled data units, wherein the swizzling of the first plurality of data units includes exchanging bits between different data units at a same bit position;
performing error correction coding on the first plurality of swizzled data units to create a first plurality of error correction bits;
swapping the bits among the first plurality of error correction bits to generate a first plurality of swizzled error correction bits;
storing the first plurality of data units and the first plurality of swizzled error correction bits in a dynamic random-access memory (DRAM);
retrieving a second plurality of data units and a second plurality of swizzled error correction bits from the DRAM;
deswizzling the second plurality of swizzled error correction bits to generate a second plurality of error correction bits;
swizzling the second plurality of data units to generate a second plurality of data units; and
performing error correction and/or error detection based on the second plurality of swizzled data units and the second plurality of error correction bits.