CPC G06F 11/0793 (2013.01) [G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G11C 8/08 (2013.01)] | 20 Claims |
1. A memory device comprising:
a normal wordline activation logic circuit configured to output a normal wordline activation signal in response to an active row address being matched;
a first redundancy circuit configured to output a post package repair (PPR) wordline activation signal and activate a PPR wordline in response to the active row address being matched; and
at least one second redundancy circuit configured to output a soft post package repair (sPPR) wordline activation signal and activate a sPPR wordline in response to the active row address being matched,
wherein the at least one second redundancy circuit is inactivated and the sPPR wordline is not activated in response to the at least one second redundancy circuit receiving old data access information.
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