US 11,789,799 B2
Protection against internal faults in burners
Erik Lang, Ettlingen (DE); and Tharsice Ball, Schirrhein (FR)
Assigned to SIEMENS AKTIENGESELLSCHAFT, Munich (DE)
Filed by Siemens Aktiengesellschaft, Munich (DE)
Filed on Jan. 11, 2021, as Appl. No. 17/145,485.
Claims priority of application No. 20151210 (EP), filed on Jan. 10, 2020.
Prior Publication US 2021/0216393 A1, Jul. 15, 2021
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G05B 19/05 (2006.01); G05B 19/10 (2006.01); G05B 23/02 (2006.01); G06F 1/28 (2006.01); G06F 13/40 (2006.01); F23N 5/24 (2006.01)
CPC G06F 11/0772 (2013.01) [G05B 19/058 (2013.01); G05B 19/10 (2013.01); G05B 23/0205 (2013.01); G05B 23/0259 (2013.01); G06F 1/28 (2013.01); G06F 11/0724 (2013.01); G06F 11/0751 (2013.01); G06F 13/4022 (2013.01); F23N 5/242 (2013.01); F23N 5/245 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A switching arrangement comprising:
a first processor and a second processor each comprising a first input;
an OR gate with an output, a first input, and a second input;
a first position feedback device; and
a first switch;
wherein the OR gate is in operative communication with the first switch via the output of the OR gate;
wherein the first processor is in operative communication with the OR gate via the first input of the OR gate and the second processor is in operative communication with the OR gate via the second input of the OR gate;
wherein at least one of the processor is programmed to send a digital ON signal to the OR gate and the OR gate is configured to actuate the first switch on receiving the digital ON signal;
wherein the first position feedback device is associated with the first switch and is in operative communication with the first input of the first processor and with the first input of the second processor;
wherein the first processor and the second processor are communicatively interconnected and each programmed to:
read a first position signal from the first position feedback device;
send the first position signal to the other processor;
compare the first position signal read by the respective processor to the first position signal received from the other processor; and
generate an error message if the first position signal read is different from the first position signal received.