US 11,789,740 B2
Performing branch predictor training using probabilistic counter updates in a processor
Rami Mohammad Al Sheikh, Morrisville, NC (US); Michael Scott McIlvaine, Raleigh, NC (US); and Daren Eugene Streett, Cary, NC (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Nov. 24, 2021, as Appl. No. 17/535,359.
Prior Publication US 2023/0161595 A1, May 25, 2023
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3844 (2013.01) [G06F 9/3806 (2013.01); G06F 9/3848 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A hardware branch predictor training circuit, configured to:
determine whether a first branch prediction generated for a first conditional branch instruction by a branch predictor circuit of a processor is correct;
based on determining whether the first branch prediction is correct, probabilistically update a first counter, corresponding to the first branch prediction, of a plurality of counters of a first branch predictor table of a plurality of branch predictor tables based on a table-specific probability value corresponding to the first branch predictor table;
determine whether a third branch prediction generated for a third conditional branch instruction by the branch predictor circuit is correct; and
based on determining whether the third branch prediction is correct:
determine that a prediction accuracy corresponding to the first branch predictor table is below an accuracy threshold; and
responsive to determining that the prediction accuracy corresponding to the first branch predictor table is below the accuracy threshold, non-probabilistically update a third counter, corresponding to the third branch prediction, of the plurality of counters of the first branch predictor table;
wherein the table-specific probability value is one of a plurality of table-specific probability values that each correspond to a branch predictor table of the plurality of branch predictor tables.