US 11,789,738 B2
Software instruction set update of memory die using page buffers
Scott Anthony Stoller, Boise, ID (US); Douglas Eugene Majerus, Boise, ID (US); and Qisong Lin, El Dorado Hills, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 14, 2022, as Appl. No. 17/986,318.
Application 17/986,318 is a continuation of application No. 16/902,009, filed on Jun. 15, 2020, granted, now 11,500,637.
Prior Publication US 2023/0073018 A1, Mar. 9, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/445 (2018.01); G06F 3/06 (2006.01); G06F 8/65 (2018.01)
CPC G06F 9/30181 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 8/65 (2013.01); G06F 9/445 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a NAND memory die, the memory die comprising one or more hardware processors configured to perform one or more operations by a set of instructions and configured to perform operations of:
receiving a command from a memory controller to update the set of instructions, the command including a location of an updated set of instructions in a page buffer of the memory die;
responsive to receiving the command, updating the set of instructions based upon the updated set of instructions in the page buffer; and
executing the updated set of instructions in the page buffer.