CPC G06F 9/30054 (2013.01) [G06F 9/30076 (2013.01); G06F 9/30145 (2013.01); G06F 9/3851 (2013.01); G06F 9/3857 (2013.01); G06F 9/3861 (2013.01); G06F 21/52 (2013.01); G06F 9/3005 (2013.01); G06F 9/3012 (2013.01); G06F 21/71 (2013.01)] | 8 Claims |
1. A processor comprising:
a storage to store state information;
first circuitry to decode instructions, including a first indirect control transfer instruction, a second indirect control transfer instruction of a different type than the first indirect control transfer instruction, and a control transfer termination instruction, wherein the control transfer termination instruction comprises an opcode and has a length of at least four bytes;
second circuitry coupled to the first circuitry and the storage to execute the first indirect control transfer instruction to
perform an indirect control transfer to a target instruction, wherein a two bit field having a first value is to be stored in the storage in response to the first indirect control transfer instruction, and wherein the first value of the two bit field is different than a second value of the two bit field to be stored in the storage in response to the second indirect control transfer instruction; and
third circuitry, responsive to the first indirect control transfer instruction, to:
determine whether the target instruction is a valid control transfer point for the first indirect control transfer instruction, wherein for the control transfer termination instruction to be the valid control transfer point for the first indirect control transfer instruction depends on a value of the two bit field;
in response to a determination the target instruction is not the valid control transfer point, cause a first exception to be raised; and
in response to a determination the target instruction is the valid control transfer point, not cause the first exception to be raised.
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