| CPC G06F 9/3001 (2013.01) [G06F 7/5443 (2013.01); G06F 9/3869 (2013.01); G06F 9/4881 (2013.01)] | 20 Claims |
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1. An instruction processing apparatus, comprising:
a plurality of instruction buffers,
a plurality of hardware registers,
a selector,
a parser, and
an operation circuit,
wherein:
the selector is configured to:
receive a command and data,
parse out a command type and a buffer identifier from the received command,
determine whether the command type is a configuration type or an execution type,
in response to the command type being the configuration type, send the received data and the buffer identifier to the parser, and
in response to the command type being the execution type, send the buffer identifier to the operation circuit;
the parser is configured to:
parse out an instruction sequence from the received data,
store the instruction sequence into one of the plurality of instruction buffers that corresponds to the buffer identifier, and
store an operand of each instruction of the instruction sequence into a corresponding entry of the plurality of hardware registers; and
the operation circuit is configured to:
sequentially execute instructions of the instruction sequence stored in the instruction buffer corresponding to the buffer identifier,
generate a control signal for each executed instruction, and
send the control signal of each executed instruction and the operand of the executed instruction stored in the plurality of hardware registers to a plurality of execution units, for each of the plurality of execution units to perform a corresponding operation based on the received control signal and the operand.
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