US 11,789,730 B2
Electronic control device and control method
Taisuke Ueta, Tokyo (JP); Tatsuya Horiguchi, Tokyo (JP); Kenichi Shimbo, Tokyo (JP); and Hideyuki Sakamoto, Hitachinaka (JP)
Assigned to Hitachi Astemo, Ltd., Hitachinaka (JP)
Appl. No. 17/428,107
Filed by Hitachi Astemo, Ltd., Hitachinaka (JP)
PCT Filed Jan. 29, 2020, PCT No. PCT/JP2020/003150
§ 371(c)(1), (2) Date Aug. 3, 2021,
PCT Pub. No. WO2020/162280, PCT Pub. Date Aug. 13, 2020.
Claims priority of application No. 2019-020509 (JP), filed on Feb. 7, 2019.
Prior Publication US 2022/0058020 A1, Feb. 24, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 9/445 (2018.01)
CPC G06F 9/3001 (2013.01) [G06F 9/345 (2013.01); G06F 9/3877 (2013.01); G06F 9/44505 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An electronic control device comprising:
a processing control unit; and
an information acquisition unit, wherein
the information acquisition unit collects external environment information and transfers the external environment information to the processing control unit,
the processing control unit includes a first processor, a second processor, a storage unit, and a reconfigurable logic circuit,
the processing control unit executes arithmetic processing by a non-redundant processing configuration that executes non-redundant processing using the first processor and the second processor, and arithmetic processing by a redundant processing configuration that executes redundant processing using the first processor and the second processor,
the processing control unit stores a result of arithmetic processing by the non-redundant processing configuration in the storage unit, individually performs arithmetic processing using the stored result in both the first processor and the second processor by arithmetic processing by the redundant processing configuration, and performs determination for an arithmetic processing result by the non-redundant processing configuration based on an arithmetic result by the first processor and an arithmetic result by the second processor, and
the reconfigurable logic circuit
executes processing together with the first processor and the second processor in the non-redundant processing configuration, and
divides a circuit into a first region and a second region by reconfiguration in the redundant processing configuration and executes processing individually by causing the first processor and the first region and the second processor and the second region to be redundant.