US 11,789,655 B2
Efficient and low latency memory access scheduling
Guanhao Shen, Austin, TX (US); and Ravindra Nath Bhargava, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 30, 2021, as Appl. No. 17/490,684.
Application 17/490,684 is a continuation in part of application No. 17/218,703, filed on Mar. 31, 2021.
Prior Publication US 2022/0317934 A1, Oct. 6, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a command queue for receiving and storing decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command; and
an arbiter coupled to said command queue for picking selected decoded memory commands among said decoded memory commands from said command queue for dispatch to said memory system by comparing said priority and said age for decoded memory commands having a first type,
wherein said arbiter is operable to:
detect when said command queue receives an elevated priority read command during a streak of page-hit write accesses, wherein said elevated priority read command is one of a page-miss and a page conflict; and
perform at least one pre-work action as an action that reduces a latency of said elevated priority read command when said arbiter subsequently switches from picking page-hit write accesses to picking said elevated priority read command.