US 11,789,647 B2
Address verification for a memory device
Aaron P. Boehm, Boise, ID (US); and Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 13, 2020, as Appl. No. 17/98,096.
Claims priority of provisional application 62/951,517, filed on Dec. 20, 2019.
Prior Publication US 2021/0191660 A1, Jun. 24, 2021
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0671 (2013.01); G06F 2212/7209 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, at a memory device that comprises an array of memory cells, a command to write data to an address within the array, wherein the address comprises a plurality of bits;
calculating one or more parity bits based at least in part on the plurality of bits of the address;
writing the data to a first portion of a page of memory cells in a first subarray of the array based at least in part on the command;
writing the address to a second portion of the page of memory cells; and
writing an indication of the address to a second subarray of the array based at least in part on the command, wherein the indication of the address comprises the one or more parity bits and one or more double-error-detecting (DED) bits, the indication of the address being for verifying that a correct address is accessed.