US 11,789,644 B2
Memory centric system incorporating computational memory
Robert D. Norman, Pendleton, OR (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Oct. 6, 2022, as Appl. No. 17/938,638.
Application 17/938,638 is a continuation of application No. 17/176,860, filed on Feb. 16, 2021, granted, now 11,507,301.
Claims priority of provisional application 62/980,586, filed on Feb. 24, 2020.
Claims priority of provisional application 62/980,600, filed on Feb. 24, 2020.
Prior Publication US 2023/0037047 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/061 (2013.01); G06F 3/0673 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory processor array, comprising:
a plurality of memory cubes, each memory cube comprising a memory module coupled to and in communication with a processor mini core to form a computational memory, each memory module comprising one or more quasi-volatile memory circuits interconnected to at least one memory controller circuit,
wherein each processor mini core in each memory cube operates on data stored in the associated memory module and the plurality of memory cubes operates in parallel to perform computation or processing tasks.