CPC G06F 3/0655 (2013.01) [G06F 3/061 (2013.01); G06F 3/0673 (2013.01)] | 13 Claims |
1. A memory processor array, comprising:
a plurality of memory cubes, each memory cube comprising a memory module coupled to and in communication with a processor mini core to form a computational memory, each memory module comprising one or more quasi-volatile memory circuits interconnected to at least one memory controller circuit,
wherein each processor mini core in each memory cube operates on data stored in the associated memory module and the plurality of memory cubes operates in parallel to perform computation or processing tasks.
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