US 11,789,640 B2
Estimation of read level thresholds using a data structure
Michael Sheperek, Longmont, CO (US); Larry J. Koudele, Erie, CO (US); and Bruce A. Liikanen, Berthoud, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 10, 2021, as Appl. No. 17/316,612.
Application 17/316,612 is a continuation of application No. 16/514,588, filed on Jul. 17, 2019, granted, now 11,003,383.
Prior Publication US 2021/0334035 A1, Oct. 28, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/26 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory sub-system comprising:
a memory device of the memory sub-system; and
a processing device of the memory sub-system, operatively coupled with the memory device, to perform operations comprising:
determining, during an operational mode of the memory sub-system, a data structure that identifies a shape of a region that is located between programming distributions of the memory device based on a plurality of error counts and a plurality of read level thresholds at the region;
selecting, during the operational mode of the memory sub-system, an estimator type from a plurality of estimator types corresponding with the data structure based on a shape type of the region;
estimating, during the operational mode, a read level threshold of the plurality of read level thresholds using the selected estimator type; and
performing, during the operational mode, a read operation at the memory device using the read level threshold estimated using the selected estimator type.