US 11,789,610 B2
3D-stacked memory with reconfigurable compute logic
Mu-Tien Chang, San Jose, CA (US); Prasun Gera, Atlanta, GA (US); Dimin Niu, Sunnyvale, CA (US); and Hongzhong Zheng, Sunnyvale, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 21, 2021, as Appl. No. 17/353,393.
Application 17/353,393 is a continuation of application No. 15/143,248, filed on Apr. 29, 2016, granted, now 11,079,936.
Claims priority of provisional application 62/301,966, filed on Mar. 1, 2016.
Prior Publication US 2021/0311634 A1, Oct. 7, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 15/78 (2006.01); G06F 9/30 (2018.01)
CPC G06F 3/0605 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0625 (2013.01); G06F 3/0635 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 9/30196 (2013.01); G06F 15/785 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first memory portion for translating a memory command into a logic command to perform an arithmetic operation; and
an interface for receiving a configuration command from a host to configure the memory device to operate in a processor-in-memory (PIM) mode,
wherein the memory device, operating in the PIM mode and receiving at least one of a “read” command, an “activate” command, a “precharge” command, or a “refresh” command as the memory command, is configured to compute data by performing a memory access operation comprising at least one of an “add” command, a “multiply” command, a “divide” command, a “compare” command, a “shift” command, an “and” command, an “or” command, or an “xor” command as the logic command.