US 11,789,516 B2
Device, method and system for transparently changing a frequency of an interconnect fabric
Chen Ranel, Shoham (IL); Christopher J. Lake, Folsom, CA (US); Hem Doshi, Folsom, CA (US); Ido Melamed, Kfar-Saba (IL); Vijay Degalahal, Bangalore (IN); Yevgeni Sabin, Haifa (IL); Reena Patel, El Dorado Hills, CA (US); Yoav Ben-Raphael, Haifa (IL); Nimrod Angel, Haifa (IL); Efraim Rotem, Haifa (IL); Shaun Conrad, El Dorado Hills, CA (US); Tomer Ziv, Rishon Lezion (IL); Nir Rosenzweig, Givat Ella (IL); Esfir Natanzon, Haifa (IL); Yoni Aizik, Haifa (IL); Arik Gihon, Rishon le Zion (IL); and Natanel Abitan, Beit Yitzhak (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/440,688
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed May 22, 2020, PCT No. PCT/US2020/034346
§ 371(c)(1), (2) Date Sep. 17, 2021,
PCT Pub. No. WO2020/242991, PCT Pub. Date Dec. 3, 2020.
Claims priority of provisional application 62/852,948, filed on May 24, 2019.
Prior Publication US 2022/0179473 A1, Jun. 9, 2022
Int. Cl. G06F 1/00 (2006.01); G06F 1/324 (2019.01)
CPC G06F 1/324 (2013.01) 20 Claims
OG exemplary drawing
 
1. A device comprising:
an interconnect fabric comprising one or more nodes;
an end point device coupled to the interconnect fabric via an asynchronous device;
a clock controller coupled to provide a clock signal to the one or more nodes, wherein, based on the clock signal, the one or more nodes are to communicate with the end point device via the asynchronous device while a first clock domain comprises the one or more nodes, and while a second clock domain comprises the end point device; and
a power management (PM) controller to communicate a control signal to the clock controller while the clock signal is cycled at a first frequency, wherein the control signal indicates that the first clock domain is to be transitioned from the first frequency to a second frequency;
wherein, in response to the control signal, the clock controller is to stall the clock signal throughout a period of time which is equal to or greater than a duration of three cycles of a lower one of the first frequency or the second frequency, and after the period of time, to cycle the clock signal at the second frequency.