CPC G06F 1/3234 (2013.01) [G06F 1/06 (2013.01); G06F 1/10 (2013.01); G06F 1/206 (2013.01); G06F 1/3237 (2013.01); G06F 1/3243 (2013.01); G06F 13/42 (2013.01); H04J 3/0658 (2013.01); H04J 3/14 (2013.01); H04L 49/109 (2013.01); Y02D 10/00 (2018.01)] | 24 Claims |
1. A system on chip (SoC) comprising:
a plurality of intellectual property (IP) blocks;
a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks, the at least one of the IP blocks is configured to provide a request signal to the CMU indicating the at least one of the IP blocks desires to enter a selected one of a sleep mode and an active mode; and
a power management unit (PMU) configured to control a power supply to the SoC;
wherein the PMU is configured to cut off the power supply to the SoC by turning off a power control circuit if none of the plurality of IP blocks provide the request signal to the CMU within a pre-defined period of time.
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