US 11,789,515 B2
Semiconductor device
Jae Gon Lee, Yongin-si (KR); Ah Chan Kim, Hwaseong-si (KR); Jin Ook Song, Seoul (KR); Jae Young Lee, Hwaseong-si (KR); and Youn Sik Choi, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 28, 2022, as Appl. No. 17/731,953.
Application 17/731,953 is a continuation of application No. 17/159,318, filed on Jan. 27, 2021, granted, now 11,340,685.
Application 17/159,318 is a continuation of application No. 16/416,600, filed on May 20, 2019, granted, now 10,969,854, issued on Apr. 6, 2021.
Application 16/416,600 is a continuation of application No. 15/414,969, filed on Jan. 25, 2017, granted, now 10,296,065, issued on May 21, 2019.
Claims priority of provisional application 62/286,860, filed on Jan. 25, 2016.
Claims priority of provisional application 62/286,873, filed on Jan. 25, 2016.
Claims priority of application No. 10-2017-0010943 (KR), filed on Jan. 24, 2017; and application No. 10-2017-0010945 (KR), filed on Jan. 24, 2017.
Prior Publication US 2022/0261061 A1, Aug. 18, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 1/3234 (2019.01); G06F 1/06 (2006.01); G06F 13/42 (2006.01); H04J 3/06 (2006.01); H04J 3/14 (2006.01); H04L 49/109 (2022.01); G06F 1/20 (2006.01); G06F 1/3237 (2019.01); G06F 1/10 (2006.01)
CPC G06F 1/3234 (2013.01) [G06F 1/06 (2013.01); G06F 1/10 (2013.01); G06F 1/206 (2013.01); G06F 1/3237 (2013.01); G06F 1/3243 (2013.01); G06F 13/42 (2013.01); H04J 3/0658 (2013.01); H04J 3/14 (2013.01); H04L 49/109 (2013.01); Y02D 10/00 (2018.01)] 24 Claims
OG exemplary drawing
 
1. A system on chip (SoC) comprising:
a plurality of intellectual property (IP) blocks;
a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks, the at least one of the IP blocks is configured to provide a request signal to the CMU indicating the at least one of the IP blocks desires to enter a selected one of a sleep mode and an active mode; and
a power management unit (PMU) configured to control a power supply to the SoC;
wherein the PMU is configured to cut off the power supply to the SoC by turning off a power control circuit if none of the plurality of IP blocks provide the request signal to the CMU within a pre-defined period of time.