US 11,789,513 B1
Power management and current/ramp detection mechanism
Atul Bhattarai, San Jose, CA (US); Srinivas Sripada, Roseville, CA (US); Avinash Sodani, San Jose, CA (US); Michael Dudek, Mission Viejo, CA (US); Darren Walworth, Yorba Linda, CA (US); Roshan Fernando, Beaverton, OR (US); James Irvine, Gilbert, AZ (US); and Mani Gopal, San Ramon, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on May 27, 2022, as Appl. No. 17/827,508.
Application 17/827,508 is a continuation of application No. 17/086,264, filed on Oct. 30, 2020, granted, now 11,507,170.
Claims priority of provisional application 62/966,909, filed on Jan. 28, 2020.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3206 (2019.01); G06F 11/30 (2006.01)
CPC G06F 1/3206 (2013.01) [G06F 11/3062 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a multicore chip comprising a plurality of cores configured to perform one or more power-consuming operations;
a power monitoring module configured to measure power consumption of the multicore chip; and
a power throttling module configured to initiate a power throttling for the multicore chip if the measured power consumption exceeds a first threshold, wherein the power throttling module is configured to prevent at least one or more cores of the multicore chip from processing commands responsive to the initiating the power throttling, and wherein the power throttling module is further configured to terminate power throttling after a predetermined amount of time has lapsed.