US 11,789,306 B2
Display device and manufacturing method thereof
Hajime Kimura, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Mar. 7, 2022, as Appl. No. 17/688,471.
Application 17/688,471 is a continuation of application No. 16/988,758, filed on Aug. 10, 2020, granted, now 11,269,214.
Application 16/988,758 is a continuation of application No. 16/547,752, filed on Aug. 22, 2019, granted, now 10,739,637, issued on Aug. 11, 2020.
Application 16/547,752 is a continuation of application No. 16/502,063, filed on Jul. 3, 2019, granted, now 10,444,564, issued on Oct. 15, 2019.
Application 16/502,063 is a continuation of application No. 15/644,895, filed on Jul. 10, 2017, abandoned.
Application 15/644,895 is a continuation of application No. 14/819,595, filed on Aug. 6, 2015, granted, now 9,703,140, issued on Jul. 11, 2017.
Application 14/819,595 is a continuation of application No. 14/153,163, filed on Jan. 13, 2014, abandoned.
Application 14/153,163 is a continuation of application No. 12/730,566, filed on Mar. 24, 2010, granted, now 8,634,044, issued on Jan. 21, 2014.
Application 12/730,566 is a continuation of application No. 11/614,809, filed on Dec. 21, 2006, granted, now 7,821,613, issued on Oct. 26, 2010.
Claims priority of application No. 2005-378778 (JP), filed on Dec. 28, 2005.
Prior Publication US 2022/0326567 A1, Oct. 13, 2022
Int. Cl. G02F 1/1335 (2006.01); B82Y 20/00 (2011.01); G02F 1/1333 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01)
CPC G02F 1/133555 (2013.01) [B82Y 20/00 (2013.01); G02F 1/1333 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/133371 (2013.01); G02F 1/136286 (2013.01); G02F 1/136231 (2021.01); G02F 2202/36 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor film;
a gate insulating film over the semiconductor film;
a gate wiring over and in contact with an upper surface of the gate insulating film;
a first metal film over and in contact with the upper surface of the gate insulating film;
a first insulating film over the gate wiring and the first metal film;
a source line over the first insulating film; and
a second metal film over the first insulating film,
wherein the semiconductor film comprises polycrystalline silicon,
wherein the source line is in direct contact with the semiconductor film,
wherein the semiconductor film comprises a first channel formation region, a second channel formation region, a first region, and a second region;
wherein the gate wiring comprises a third region and a fourth region,
wherein the third region of the gate wiring overlaps the first channel formation,
wherein the fourth region of the gate wiring overlaps the second channel formation,
wherein the first region of the semiconductor film has a first width which is parallel to a direction in which the source line extends, and a second width which is perpendicular to the first width,
wherein the first width of the first region of the semiconductor film is longer than the second width of the first region of the semiconductor film,
wherein the second region of the semiconductor film has a third width which is parallel to a direction in which the source line extends, and a fourth width which is perpendicular to the third width,
wherein the fourth width of the second region of the semiconductor film is longer than the third width of the second region of the semiconductor film,
wherein the first metal film has a fifth width which is parallel to a direction in which the source line extends, and a sixth width which is perpendicular to the fifth width of the first metal film,
wherein the sixth width of the first metal film is longer than the fifth width of the first metal film,
wherein the second metal film overlaps the first metal film with the first insulating film interposed therebetween,
wherein the second metal film overlaps the first region of the semiconductor film,
wherein a long axis of the second metal film is parallel to a long axis of the gate wiring, and
wherein the first insulating film comprises a region which is not overlapped by the second metal film and overlaps the gate insulating film.