US 11,789,137 B2
FMCW chirp bandwidth control
Karthik Subburaj, Karnataka (IN); Sreekiran Samala, Plano, TX (US); and Indu Prathapan, Karnataka (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Dec. 30, 2020, as Appl. No. 17/138,549.
Prior Publication US 2022/0206133 A1, Jun. 30, 2022
Int. Cl. H03L 7/099 (2006.01); H03L 7/087 (2006.01); G01S 13/34 (2006.01); G01S 7/03 (2006.01); H03C 3/09 (2006.01); G01S 7/35 (2006.01)
CPC G01S 13/345 (2013.01) [G01S 7/032 (2013.01); G01S 7/352 (2013.01); H03C 3/0925 (2013.01); H03L 7/087 (2013.01); H03L 7/099 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A frequency modulated continuous wave (FMCW) synthesizer, comprising:
a phase locked loop (PLL) including:
a frequency divider including a control input, a frequency divider input, and a frequency divider output;
a control voltage generator (CVG) including a CVG input coupled to the frequency divider output, wherein the CVG is configured to generate a control voltage in response to the CVG input; and
a voltage controlled oscillator (VCO) including a VCO input coupled to the CVG, wherein the VCO further includes a VCO output coupled to the frequency divider input, and wherein the VCO is configured to output a FMCW output signal having a FMCW output frequency in response to the VCO input; and
a control engine including a control output coupled to the control input of the frequency divider, the control engine configured to control the PLL so that the FMCW output frequency:
from a first time to a second time, is a first idle frequency;
from the second time to a third time, changes at a specified first rate;
from the third time to a fourth time, changes at a specified second rate, wherein the specified first rate is different from the specified second rate; and
from the fourth time to a fifth time, is a second idle frequency,
wherein the first idle frequency is different from the second idle frequency.