US 10,798,821 B2
Circuit board having a passive device inside a via
Carlos Gomez, Round Rock, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Apr. 2, 2016, as Appl. No. 15/89,482.
Prior Publication US 2017/0290162 A1, Oct. 5, 2017
Int. Cl. H05K 1/18 (2006.01); H05K 1/11 (2006.01); H05K 1/02 (2006.01); H05K 3/34 (2006.01); H05K 3/42 (2006.01)
CPC H05K 1/184 (2013.01) [H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H05K 1/181 (2013.01); H05K 3/34 (2013.01); H05K 3/429 (2013.01); Y02P 70/611 (2015.11)] 15 Claims
OG exemplary drawing
 
1. A circuit board comprising:
a plurality of insulating layers provided in a stack, including a first outermost insulating layer having a top surface of the stack, a second outermost insulating layer having a bottom surface of the stack, and one or more intermediate insulating layers between the first and second outermost insulating layers, the plurality of insulating layers being formed of non-conductive materials;
a via that extends from the top surface of the stack to the bottom surface of the stack; and
a passive device provided in the via, spanning a portion but not an entire length of the via, with a first terminal disposed at a first end of the passive device immediately adjacent to the top surface of the stack, and a second terminal disposed at a second end of the passive device immediately adjacent to a top surface of one of the one or more intermediate insulating layers;
a first connector structure to couple the first terminal of the passive device to a conductive trace on the top surface of the stack, and a second connector structure to couple the second terminal to a conductive trace on the immediately adjacent top surface of the one of intermediate insulating layer; and
a space disposed along a vertical side of the via separating the first and second connector structures.