US 11,758,819 B2
Magneto-resistive random access memory with laterally-recessed free layer
Oscar van der Straten, Guilderland Center, NY (US); Koichi Motoyama, Clifton Park, NY (US); Kenneth Chun Kuen Cheng, Shatin (HK); Joseph F. Maniscalco, Lake Katrine, NY (US); and Chih-Chao Yang, Glenmont, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 15, 2020, as Appl. No. 17/122,809.
Prior Publication US 2022/0190235 A1, Jun. 16, 2022
Int. Cl. H10N 50/10 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC H10N 50/10 (2023.02) [G11C 11/161 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a bottom electrode above an electrically conductive structure, the electrically conductive structure being embedded within an interconnect dielectric material;
a diffusion barrier liner located on a bottom surface and lateral sidewalls of the electrically conductive structure; and
a magnetic tunnel junction stack above the bottom electrode, the magnetic tunnel junction stack comprising a magnetic reference layer above the bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a magnetic free layer above the tunnel barrier layer, the magnetic free layer being laterally recessed with respect to the tunnel barrier layer, the magnetic free layer surrounded by sidewall spacers to confine an active region formed by the magnetic free and the tunnel barrier layer.