CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02)] | 10 Claims |
1. A memory device, comprising:
a substrate having an upper surface;
a laminated structure disposed on the substrate, the laminated structure comprising a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction vertical to the upper surface; and
a memory string accommodated in the laminated structure along the first direction, the memory string comprising a memory layer and a channel layer, and the memory layer is disposed between the laminated structure and the channel layer,
wherein at least a portion of the memory layer and the insulating layers are overlapped along the first direction, the at least a portion of the memory layer comprises a plurality of memory portions, each of the memory portions corresponds to one layer of the conductive layers, and each of the memory portions completely surrounds the channel layer.
|