US 11,758,711 B2
Thin-film transistor embedded dynamic random-access memory with shallow bitline
Yih Wang, Portland, OR (US); Abhishek A. Sharma, Hillsboro, OR (US); Tahir Ghani, Portland, OR (US); Allen B. Gardiner, Portland, OR (US); Travis W. Lajoie, Forest Grove, OR (US); Pei-Hua Wang, Beaverton, OR (US); Chieh-Jen Ku, Portland, OR (US); Bernhard Sell, Portland, OR (US); Juan G. Alzate-Vinasco, Tigard, OR (US); and Blake C. Lin, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 17, 2022, as Appl. No. 17/696,945.
Application 17/696,945 is a continuation of application No. 15/956,379, filed on Apr. 18, 2018, granted, now 11,329,047.
Prior Publication US 2022/0208770 A1, Jun. 30, 2022
Int. Cl. H01L 27/108 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01)
CPC H10B 12/315 (2023.02) [H01L 23/528 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 27/0605 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 27/1262 (2013.01); H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a transistor, comprising a first region and a second region, wherein one of the first region and the second region is a source region of the transistor and another one of the first region and the second region is a drain region of the transistor;
a capacitor coupled to the first region;
a bitline coupled to the second region;
an electrically conductive line; and
a bridge via to electrically couple the bitline and the electrically conductive line, where an electrically conductive material of the bridge via fills a gap between the bitline and the electrically conductive line.