CPC H10B 12/30 (2023.02) [G11C 5/10 (2013.01); G11C 11/221 (2013.01); G11C 11/4023 (2013.01); H10B 53/20 (2023.02)] | 20 Claims |
20. A system comprising:
a memory to store one or more instructions on the memory;
a processor circuitry to execute the one or more instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
a via that extends along a y-plane, wherein the y-plane is orthogonal to an x-plane, wherein the via couples to a first metal layer;
a first capacitor including a non-linear polar material, wherein the first capacitor includes an electrode coupled to the via, and wherein the electrode is substantially in a middle of the first capacitor;
a second capacitor including a linear dielectric material, wherein the electrode passes through a middle of the second capacitor;
a first plate-line that extends along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first plate-line is on an outer portion of the first capacitor; and
a second plate-line that extends along the x-plane or the z-plane, wherein the second plate-line is on an output portion of the second capacitor, and wherein the second plate-line has a voltage complementary to a voltage on the first plate-line.
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