US 11,758,708 B1
Stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell
Rajeev Kumar Dokania, Beaverton, OR (US); Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 2, 2021, as Appl. No. 17/517,345.
Application 17/517,345 is a continuation of application No. 17/516,293, filed on Nov. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H10B 12/00 (2023.01); G11C 11/402 (2006.01); G11C 11/22 (2006.01); G11C 5/10 (2006.01); H10B 53/20 (2023.01)
CPC H10B 12/30 (2023.02) [G11C 5/10 (2013.01); G11C 11/221 (2013.01); G11C 11/4023 (2013.01); H10B 53/20 (2023.02)] 20 Claims
OG exemplary drawing
 
20. A system comprising:
a memory to store one or more instructions on the memory;
a processor circuitry to execute the one or more instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
a via that extends along a y-plane, wherein the y-plane is orthogonal to an x-plane, wherein the via couples to a first metal layer;
a first capacitor including a non-linear polar material, wherein the first capacitor includes an electrode coupled to the via, and wherein the electrode is substantially in a middle of the first capacitor;
a second capacitor including a linear dielectric material, wherein the electrode passes through a middle of the second capacitor;
a first plate-line that extends along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first plate-line is on an outer portion of the first capacitor; and
a second plate-line that extends along the x-plane or the z-plane, wherein the second plate-line is on an output portion of the second capacitor, and wherein the second plate-line has a voltage complementary to a voltage on the first plate-line.