US 11,758,185 B2
Encoder, decoder, encoding method, and decoding method
Kiyofumi Abe, Osaka (JP); Takahiro Nishi, Nara (JP); Tadamasa Toma, Osaka (JP); and Ryuichi Kanoh, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Jul. 19, 2021, as Appl. No. 17/379,327.
Application 17/379,327 is a continuation of application No. 17/023,968, filed on Sep. 17, 2020, granted, now 11,102,512.
Application 17/023,968 is a continuation of application No. 16/407,550, filed on May 9, 2019, granted, now 10,812,827, issued on Oct. 20, 2020.
Claims priority of provisional application 62/670,235, filed on May 11, 2018.
Prior Publication US 2021/0352322 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/159 (2014.01); H04N 19/593 (2014.01); H04N 19/44 (2014.01); H04N 19/176 (2014.01)
CPC H04N 19/593 (2014.11) [H04N 19/176 (2014.11); H04N 19/44 (2014.11)] 6 Claims
OG exemplary drawing
 
1. A decoder for decoding a block, comprising:
circuitry; and
memory,
wherein, using the memory, the circuitry:
prohibits a first mode in which the block is to be split multiple times to generate first blocks; and
performs a second mode different from the first mode to split the block in order to generate second blocks, wherein
arrangement, shapes, and scan order of the first blocks are identical to arrangement, shapes, and scan order of the second blocks, respectively.