CPC H04L 49/9063 (2013.01) [H04L 43/0882 (2013.01); H04L 47/627 (2013.01); H04L 47/826 (2013.01)] | 21 Claims |
1. An apparatus comprising:
a plurality of memory instances that form a buffer, each of the memory instances comprising a plurality of entries configured to store storage data units (“SDUs”), each of the entries configured to store a single SDU;
buffer management logic that:
arranges the memory instances into overlapping logical banks;
arranges the logical banks into views of non-overlapping logical banks, at least some of the memory instances belonging to logical banks in two or more of the views;
assigns the views to different destinations;
two or more egress packet processors that process transport data units (“TDUs”) and forward the TDUs to external destinations, wherein the views include two different views respectively assigned to two different egress packet processors in the egress packet processors;
read logic that reads one or more of the TDUs from the buffer by performing:
receiving a request for reading a TDU;
identifying a logical bank in which the TDU is stored, the logical bank having been selected by a previous TDU write operation based on a view, of the views, assigned to a destination associated with the TDU;
identifying one or more SDUs assigned to the TDU in the logical bank;
at a scheduled access period, reading the one or more SDUs assigned to the TDU in the logical bank.
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