US 11,757,798 B2
Management of a buffered switch having virtual channels for data transmission within a network
John Coddington, Cedar Park, TX (US)
Assigned to ARTERIS, INC., Campbell, CA (US)
Filed by ARTERIS, INC., Campbell, CA (US)
Filed on Dec. 28, 2020, as Appl. No. 17/134,544.
Prior Publication US 2022/0210096 A1, Jun. 30, 2022
Int. Cl. H04L 41/5054 (2022.01); H04L 49/9005 (2022.01); H04L 49/9047 (2022.01); H04L 43/0852 (2022.01); H04L 45/00 (2022.01); H04L 45/44 (2022.01)
CPC H04L 49/9005 (2013.01) [H04L 43/0852 (2013.01); H04L 45/20 (2013.01); H04L 45/44 (2013.01); H04L 49/9047 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A buffered switch circuit in the network-on-chip (NoC) for data transmission, the buffered switch comprising:
an input for receiving a plurality of transactions in the form of data packets;
a plurality of internal channels, which utilize the buffered switch's bandwidth and are communicatively coupled to the input, wherein each of the plurality of internal channels has a plurality of routes and each of the plurality of routes are internally separate from one another thereby eliminating the need for credits;
at least one buffer communicatively coupled to the plurality of internal channels, wherein the buffer is capable of storing at least one data packet of the data packets;
a plurality of switches communicatively coupled to the plurality of internal channels, wherein an end switch of the plurality of switches of a given internal channel is aware of data packets traveling along the given internal channel as the given internal channel's respective plurality of routes are internally separated;
a plurality of interfaces communicatively coupled to the plurality of switches; and
an output communicatively coupled to the plurality of interfaces such that each of the plurality of internal channels' route is separate through the buffered switch and merged at the output.