| CPC H04L 49/3072 (2013.01) [H04L 12/40071 (2013.01); H04L 49/9042 (2013.01)] | 23 Claims |
|
1. A system comprising a peripheral device including:
a memory access interface to receive from a host device: headers of respective packets, while corresponding payloads of the respective packets are stored in a host memory of the host device; and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored;
a data processing unit memory to store the received headers and the descriptors without the payloads of the respective packets; and
a data processing unit to process the received headers, and to perform any one or more of the following:
reorder the received headers thereby causing the respective packets to be reordered;
delay the received headers thereby causing sending of the respective packets to be delayed;
schedule the received headers thereby causing scheduling sending of the respective packets;
segment the received headers thereby causing the payloads of the respective packets to be segmented; and
duplicate the received headers thereby causing each of the respective packets to be sent multiple times, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the respective packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors; and
packet processing circuitry to receive the headers and payloads of the respective packets; and process the packets.
|