CPC H04L 25/03057 (2013.01) [H04L 25/03885 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a front-end circuit configured to generate an equalized signal using a plurality of signals that encode a serial data stream including a plurality of data symbols;
a summer circuit configured to combine the equalized signal and a feedback signal to generate a summation signal;
a recovery circuit configured to:
sample the summation signal to generate a plurality of data samples; and
sample a combination of the summation signal and a dither signal to generate a plurality of error samples;
an equalizer circuit including a digital-to-analog converter circuit, wherein the equalizer circuit is configured to generate the feedback signal using the plurality of data samples and the plurality of error samples; and
a dither circuit configured to activate the dither signal in response to a determination that the digital-to-analog converter circuit is saturated.
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