CPC H04L 7/0016 (2013.01) [H03K 5/082 (2013.01); H04L 25/4917 (2013.01)] | 2 Claims |
1. A method to reduce bit error rate in a PAM4 clock data recovery circuit, comprising:
determining a first target value of a first slicing level;
sweeping down from an upper voltage threshold to determine a first reference voltage that is lower than the upper voltage threshold;
detecting a first filtered output associated with the first reference voltage;
determining whether the first filtered output is higher than the first target value;
responsive to determining that the first filtered output is higher than the first target value, storing the first reference voltage value;
sweeping up from a lower voltage threshold to determine a second reference voltage that is higher than the lower voltage threshold;
detecting a second filtered output associated with the second reference voltage;
determining whether the second filtered output is lower than a second target value;
responsive to determining that the second filtered output is lower than the second target value, storing the second reference voltage value; and
averaging the stored first reference voltage value and the stored second reference voltage value to determine calculated threshold value.
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