US 11,757,609 B2
Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
Scott E. Meninger, Groton, MA (US)
Assigned to Marvell Asia Pte, Ltd., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on May 18, 2021, as Appl. No. 17/324,025.
Application 17/324,025 is a continuation of application No. 16/569,445, filed on Sep. 12, 2019, granted, now 11,044,071.
Application 16/569,445 is a continuation of application No. 16/352,180, filed on Mar. 13, 2019, granted, now 10,461,917, issued on Oct. 29, 2019.
Application 16/352,180 is a continuation of application No. 15/721,334, filed on Sep. 29, 2017, granted, now 10,291,386, issued on May 14, 2019.
Prior Publication US 2021/0273776 A1, Sep. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 7/00 (2006.01); H03L 7/197 (2006.01); G06F 1/06 (2006.01); H03L 7/00 (2006.01); H03L 7/08 (2006.01); H04L 27/227 (2006.01); H03M 9/00 (2006.01); G06F 1/10 (2006.01); H03L 7/23 (2006.01); H04L 1/00 (2006.01); H04J 3/06 (2006.01)
CPC H04L 7/0008 (2013.01) [G06F 1/06 (2013.01); H03L 7/00 (2013.01); H03L 7/08 (2013.01); H03L 7/1976 (2013.01); H03L 7/23 (2013.01); H04L 1/0065 (2013.01); H04L 27/2272 (2013.01); G06F 1/10 (2013.01); H03M 9/00 (2013.01); H04J 3/0685 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
modulating a divide value of a divider included in a fractional-N (frac-N) phase-locked loop (PLL), the frac-N PLL included in a serializer/deserializer (SerDes) lane, the SerDes lane coupled to an integer PLL having a multiplying factor; and
suppressing a portion of quantization noise introduced by modulating the divide value of the divider, the suppressing based on the multiplying factor of the integer PLL.