CPC H04L 7/0008 (2013.01) [G06F 1/06 (2013.01); H03L 7/00 (2013.01); H03L 7/08 (2013.01); H03L 7/1976 (2013.01); H03L 7/23 (2013.01); H04L 1/0065 (2013.01); H04L 27/2272 (2013.01); G06F 1/10 (2013.01); H03M 9/00 (2013.01); H04J 3/0685 (2013.01)] | 19 Claims |
1. A method comprising:
modulating a divide value of a divider included in a fractional-N (frac-N) phase-locked loop (PLL), the frac-N PLL included in a serializer/deserializer (SerDes) lane, the SerDes lane coupled to an integer PLL having a multiplying factor; and
suppressing a portion of quantization noise introduced by modulating the divide value of the divider, the suppressing based on the multiplying factor of the integer PLL.
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