CPC H04L 5/14 (2013.01) [G06F 1/3203 (2013.01); H04B 1/40 (2013.01); H04L 12/40039 (2013.01)] | 18 Claims |
1. An integrated circuit (IC), comprising:
a transceiver circuit, comprising:
control circuitry configured to generate mode control signals for controlling portions of the transceiver circuit in a mode selected from i) a data transfer mode of operation, ii) a first low power mode of operation, and iii) a second low power mode of operation; and
a transmit circuit coupled to the control circuitry, the transmit circuit being configured:
in response to receiving a first mode control signal, to enter the data transfer mode of operation, and transmit first data over a first communication channel to a link partner;
in response to receiving a second mode control signal, to enter the first low power mode of operation and transmit a first sequence of refresh signals, the first sequence of refresh signals exhibiting a first predefined refresh signal structure that is compliant with an Institute of Electrical and Electronics Engineers (IEEE) 802.3 refresh signal protocol, the refresh signals for maintaining the first communication channel in an alive state with the link partner; and
in response to receiving a third mode control signal to enter the second low power mode of operation and selectively encode information into a second sequence of refresh signals, the second sequence of refresh signals exhibiting the first predefined refresh signal structure for maintaining the first communication channel in an alive state with the link partner, the encoded information comprising information signals other than that required to maintain the first communication channel alive during the second low power mode of operation, the transmit circuit to transmit the second sequence of refresh signals including the encoded information over the first communication channel to the link partner.
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