CPC H03L 7/0818 (2013.01) [H03K 5/13 (2013.01); H03K 2005/00019 (2013.01)] | 30 Claims |
1. A delay cell for a delay locked loop, DLL, based serial link, comprising:
a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, R-DAC and the second stage comprising a current starved delay-cell.
|