US 11,757,455 B1
Low jitter delay cell
Sameer Wadhwa, San Diego, CA (US); and Lennart Karl-Axel Mathe, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Oct. 13, 2022, as Appl. No. 18/46,283.
Int. Cl. H03L 7/081 (2006.01); H03K 5/13 (2014.01); H03K 5/00 (2006.01)
CPC H03L 7/0818 (2013.01) [H03K 5/13 (2013.01); H03K 2005/00019 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A delay cell for a delay locked loop, DLL, based serial link, comprising:
a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, R-DAC and the second stage comprising a current starved delay-cell.