CPC H03K 23/005 (2013.01) [H03K 23/40 (2013.01)] | 9 Claims |
1. A multi-bit gray code generation circuit comprising:
a zeroth bit gray code generation circuit configured to generate a gray code corresponding to a bit 0 of a multi-bit gray code; and
a plurality of gray code generation circuits each configured to generate a gray code corresponding to each bit higher than the bit 0 of the multi-bit gray code,
wherein each of the plurality of gray code generation circuits comprises a plurality of flip-flop circuits independent from a plurality of flip-flop circuits in other gray code generation circuits among the plurality of gray code generation circuits, and includes different number of flip-flop circuits from the other gray code generation circuits,
an output of a flip-flop circuit in a previous stage is input to a flip-flop circuit of a next stage,
an output of a flip-flop circuit of a final stage is inverted and held by a flip-flop circuit of a first stage, and
an output of one of the plurality of flip-flop circuits is output as a gray code corresponding to each bit.
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