US 11,757,452 B1
OR-and-invert logic based on a mix of majority or minority logic gate with non-linear input capacitors and other logic gates
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Darshak Doshi, Sunnyvale, CA (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Apr. 20, 2022, as Appl. No. 17/659,992.
Application 17/659,992 is a continuation of application No. 17/659,981, filed on Apr. 20, 2022.
Int. Cl. H03K 19/23 (2006.01); H03K 19/20 (2006.01); H01L 49/02 (2006.01)
CPC H03K 19/23 (2013.01) [H01L 28/55 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first capacitor to receive a first input, the first capacitor coupled to a first node;
a second capacitor to receive a second input, the second capacitor coupled to the first node;
a third capacitor to receive a third input, wherein the third capacitor is coupled to the first node;
a fourth capacitor to receive a fourth input, the fourth capacitor coupled to a second node;
a fifth capacitor to receive a fifth input, the fifth capacitor coupled to the second node;
a sixth capacitor to receive a sixth input, wherein the sixth capacitor is coupled to the second node, wherein the first input, the second input, the fourth input, and the fifth input are variable inputs, and wherein the third input and the sixth input are pulled up to a power supply level; and
a NAND gate having its inputs directly coupled to the first node and the second node.