US 11,757,449 B2
Magnetoelectric XNOR logic gate device
Nishtha Sharma Gaul, Richardson, TX (US); Andrew Marshall, Dallas, TX (US); Peter A. Dowben, Crete, NE (US); and Dmitri E. Nikonov, Beaverton, OR (US)
Assigned to BOARD OF REGENT'S OF THE UNIVERSITY OF NEBRASKA, Lincoln, NE (US); BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM, Austin, TX (US); and INTEL CORPORATION, Santa Clara, CA (US)
Filed by Board of Regents of the University of Nebraska, Lincoln, NE (US)
Filed on May 29, 2022, as Appl. No. 17/827,742.
Application 17/827,742 is a division of application No. 16/581,691, filed on Sep. 24, 2019, granted, now 11,349,480.
Claims priority of provisional application 62/735,495, filed on Sep. 24, 2018.
Prior Publication US 2022/0294448 A1, Sep. 15, 2022
Int. Cl. H03K 19/16 (2006.01); H01L 29/423 (2006.01); H03K 19/10 (2006.01); H03K 19/21 (2006.01)
CPC H03K 19/16 (2013.01) [H01L 29/42312 (2013.01); H03K 19/10 (2013.01); H03K 19/21 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A magneto-electric (ME) XNOR logic gate device, comprising:
a conducting device; and
a ME-FET coupled to the conducting device, wherein the ME-FET comprises:
a split gate;
a first gate terminal coupled to a first portion of the split gate for receiving a first input signal;
a second gate terminal coupled to a second portion of the split gate for receiving a second input signal;
a source terminal coupled to a ground line; and
a drain terminal coupled to the conducting device.