US 11,757,435 B2
Data retention circuit and method
Kai-Chi Huang, Hsinchu (TW); Yung-Chen Chien, Hsinchu (TW); Chi-Lin Liu, Hsinchu (TW); Wei-Hsiang Ma, Hsinchu (TW); Jerry Chang Jui Kao, Hsinchu (TW); Shang-Chih Hsieh, Hsinchu (TW); and Lee-Chung Lu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 28, 2022, as Appl. No. 17/815,679.
Application 17/815,679 is a continuation of application No. 17/314,370, filed on May 7, 2021, granted, now 11,456,728.
Application 17/314,370 is a continuation of application No. 16/294,726, filed on Mar. 6, 2019, granted, now 11,012,057, issued on May 18, 2021.
Claims priority of provisional application 62/651,946, filed on Apr. 3, 2018.
Prior Publication US 2022/0368318 A1, Nov. 17, 2022
Int. Cl. H03K 3/037 (2006.01); G06F 1/3237 (2019.01); H03K 3/356 (2006.01); H03K 19/00 (2006.01)
CPC H03K 3/0375 (2013.01) [G06F 1/3237 (2013.01); H03K 3/0372 (2013.01); H03K 3/356086 (2013.01); H03K 19/0016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first power node configured to have a first voltage level;
a second power node configured to have a second voltage level different from the first voltage level;
a reference node configured to have a reference voltage level;
a master latch configured to output a first data bit based on a received data bit;
a slave latch comprising:
a first inverter configured to output a second data bit based on the first data bit; and
a second inverter configured to output an output data bit based on a selected one of the first data bit or a third data bit;
a first level shifter configured to output the third data bit based on a fourth data bit; and
a retention latch configured to output the fourth data bit based on the second data bit, wherein
each of the first and second inverters and the first level shifter is coupled between the first power node and the reference node, and
the retention latch comprises a plurality of transistors coupled between the second power node and the reference node.