US 11,757,434 B2
High performance fast Mux-D scan flip-flop
Amit Agarwal, Hillsboro, OR (US); Steven Hsu, Lake Oswego, OR (US); Simeon Realov, Portland, OR (US); Mahesh Kumashikar, Bangalore (IN); and Ram Krishnamurthy, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 1, 2022, as Appl. No. 17/711,638.
Application 17/711,638 is a continuation of application No. 16/726,020, filed on Dec. 23, 2019, granted, now 11,296,681.
Prior Publication US 2022/0224316 A1, Jul. 14, 2022
Int. Cl. H03K 3/00 (2006.01); H03K 3/037 (2006.01); G01R 31/3177 (2006.01); H03K 3/038 (2006.01); H03K 19/20 (2006.01); H03K 3/3562 (2006.01)
CPC H03K 3/0372 (2013.01) [G01R 31/3177 (2013.01); H03K 3/038 (2013.01); H03K 3/35625 (2013.01); H03K 19/20 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a latch that includes a data path and a scan path, wherein the latch includes:
a transmission gate coupled on the data path between a data input and a keeper node; and
a memory circuitry coupled to the keeper node, wherein the scan path is coupled to the memory circuitry, wherein the memory circuitry includes:
a first tri-statable inverter having an input coupled to the keeper node; and
a second tri-statable inverter having an input coupled to an output of the first tri-statable inverter and the scan path, wherein an output of the second tri-statable inverter is coupled to the keeper node; and
scan clock circuitry to generate scan clock signals for a scan mode of the latch, the scan clock circuitry comprising:
an inverter having an input and an output, wherein an input of the inverter is to receive an input clock;
an AND logic coupled to the output of the inverter, wherein the AND logic is to receive a scan select signal; and
an OR logic coupled to the input of the inverter, wherein the OR logic is to receive the scan select signal.