US 11,757,411 B2
Power amplifier circuit
Satoshi Tanaka, Kyoto (JP); Satoshi Arayashiki, Kyoto (JP); Satoshi Goto, Kyoto (JP); and Yusuke Tanaka, Kyoto (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto (JP)
Filed on Dec. 29, 2022, as Appl. No. 18/147,849.
Application 18/147,849 is a continuation of application No. 17/323,505, filed on May 18, 2021, granted, now 11,558,014.
Application 17/323,505 is a continuation of application No. 16/589,369, filed on Oct. 1, 2019, granted, now 11,043,918, issued on Jun. 22, 2021.
Claims priority of application No. 2018-187387 (JP), filed on Oct. 2, 2018.
Prior Publication US 2023/0132964 A1, May 4, 2023
Int. Cl. H03F 1/02 (2006.01); H03F 3/21 (2006.01); H04W 88/02 (2009.01)
CPC H03F 1/0216 (2013.01) [H03F 3/21 (2013.01); H03F 2200/451 (2013.01); H04W 88/02 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A power amplifier circuit configured to amplify a first high-frequency differential signal that includes a first high-frequency signal and a second high-frequency signal, and to output a second high-frequency differential signal that includes a third high-frequency signal and a fourth high-frequency signal, the power amplifier circuit comprising:
a first transistor having a first terminal, a second terminal, and a third terminal, the first high-frequency signal being input to the first terminal, and the third high-frequency signal being output from the second terminal;
a second transistor having a fourth terminal, a fifth terminal, and a sixth terminal, the second high-frequency signal being input to the fourth terminal, and the fourth high-frequency signal being output from the fifth terminal;
a third transistor having a seventh terminal, an eighth terminal, and a ninth terminal, the eighth terminal being electrically connected to the fifth terminal of the second transistor, and the seventh terminal being electrically connected to the first terminal of the first transistor; and
a fourth transistor having a tenth terminal, an eleventh terminal, and a twelfth terminal, the eleventh terminal being electrically connected to the second terminal of the first transistor and the tenth terminal being electrically connected to the fourth terminal of the second transistor,
wherein the ninth terminal of the third transistor is electrically connected to the seventh terminal of the third transistor, and
wherein the twelfth terminal of the fourth transistor is electrically connected to the tenth terminal of the fourth transistor.