US 11,757,355 B1
Clock data recovery circuit including charge pump having reduced glitch current
Rajasekhar Nagulapalli, Northampton (GB); Simon Forey, Northamptonshire (GB); and Parmanand Mishra, Cupertino, CA (US)
Assigned to Marvell Asia Pte, Ltd., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Dec. 1, 2021, as Appl. No. 17/539,878.
Application 17/539,878 is a continuation of application No. 17/014,268, filed on Sep. 8, 2020, abandoned.
Application 17/014,268 is a continuation of application No. 16/284,633, filed on Feb. 25, 2019, granted, now 10,804,797, issued on Oct. 13, 2020.
Int. Cl. H02M 3/07 (2006.01); H03L 7/089 (2006.01); H04L 7/033 (2006.01)
CPC H02M 3/07 (2013.01) [H03L 7/0891 (2013.01); H04L 7/033 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A clock data recovery circuit comprising:
an input configured to receive a data signal;
a voltage controlled oscillator comprising a clock;
a phase detector configured to generate an early signal and a late signal, which are indicative of whether a phase of the clock of the voltage controlled oscillator is early or late relative to a phase of the data signal; and
a charge pump comprising
a first switch responsive to the early signal,
a second switch responsive to the late signal,
a pair of resistive elements connected in series between a drain of the first switch and a drain of the second switch to reduce glitch current at an output of the charge pump during transitions of the early signal and the late signal between high and low states, the pair of resistive elements configured to provide resistance between an output of the charge pump and the first switch and the second switch and to drive the voltage controlled oscillator, and
a capacitor connected to the drain of the first switch and to a first resistive element of the pair of resistive elements, the first resistive element limiting an amount of charge flow from the output of the charge pump back through the first resistive element to the capacitor.