US 11,757,037 B2
Epitaxial oxide plug for strained transistors
Karthik Jambunathan, Kirkland, WA (US); Biswajeet Guha, Hillsboro, OR (US); Anupama Bowonder, Portland, OR (US); Anand S. Murthy, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 6, 2022, as Appl. No. 17/569,643.
Application 17/569,643 is a continuation of application No. 16/640,465, granted, now 11,251,302, previously published as PCT/US2017/053582, filed on Sep. 27, 2017.
Prior Publication US 2022/0131007 A1, Apr. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/7846 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a nanowire comprising a semiconductor material;
a gate structure completely surrounding a channel region of the nanowire;
a source region and a drain region adjacent to, and on opposing sides of, the nanowire, the source and drain regions comprising a semiconductor composition that is distinct from the semiconductor material of the nanowire, wherein one of the source region or the drain region has a portion laterally adjacent to the nanowire; and
a plug comprising oxide material laterally adjacent to the portion of the one of the source region or the drain region laterally adjacent to the nanowire, the plug having a perovskite crystal structure.