US 11,757,030 B2
3D semiconductor device and structure with oxide bonding
Zvi Or-Bach, Haifa (IL)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Mar. 22, 2023, as Appl. No. 18/125,053.
Application 18/125,053 is a continuation in part of application No. 18/092,727, filed on Jan. 3, 2023.
Application 18/092,727 is a continuation in part of application No. 17/961,565, filed on Oct. 7, 2022, granted, now 11,575,038, issued on Feb. 7, 2023.
Application 17/961,565 is a continuation of application No. 17/384,992, filed on Jul. 26, 2021, granted, now 11,515,413, issued on Nov. 29, 2022.
Application 17/384,992 is a continuation of application No. 17/222,784, filed on Apr. 5, 2021, granted, now 11,121,246, issued on Sep. 14, 2021.
Application 17/222,784 is a continuation of application No. 17/176,146, filed on Feb. 15, 2021, granted, now 11,004,967, issued on May 11, 2021.
Application 17/176,146 is a continuation of application No. 16/226,628, filed on Dec. 19, 2018, granted, now 10,964,807, issued on Mar. 30, 2021.
Application 16/226,628 is a continuation of application No. 15/727,592, filed on Oct. 7, 2017, granted, now 10,355,121, issued on Jul. 16, 2019.
Application 15/727,592 is a continuation of application No. 15/351,389, filed on Nov. 14, 2016, granted, now 9,799,761, issued on Oct. 24, 2017.
Application 15/351,389 is a continuation of application No. 14/506,160, filed on Oct. 3, 2014, granted, now 9,496,271, issued on Nov. 15, 2016.
Application 14/506,160 is a continuation of application No. 13/792,202, filed on Mar. 11, 2013, granted, now 8,902,663, issued on Dec. 2, 2014.
Prior Publication US 2023/0223469 A1, Jul. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); G11C 16/02 (2006.01); G11C 11/404 (2006.01); G11C 11/4097 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10B 43/20 (2023.01); H10B 69/00 (2023.01); H10B 63/00 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); G11C 11/412 (2006.01); G11C 16/04 (2006.01)
CPC H01L 29/78 (2013.01) [G11C 11/404 (2013.01); G11C 11/4097 (2013.01); G11C 16/02 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/7841 (2013.01); H10B 10/12 (2023.02); H10B 12/20 (2023.02); H10B 43/20 (2023.02); H10B 63/30 (2023.02); H10B 69/00 (2023.02); G11C 11/412 (2013.01); G11C 16/0483 (2013.01); G11C 2213/71 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, the device comprising:
a first silicon layer comprising first single crystal silicon;
an isolation layer disposed over said first silicon layer;
a first metal layer disposed over said isolation layer;
a second metal layer disposed over said first metal layer;
a first level comprising a plurality of transistors, said first level disposed over said second metal layer,
wherein said isolation layer comprises an oxide to oxide bond surface,
wherein said plurality of transistors comprise a second single crystal silicon region; and
a third metal layer disposed over said first level,
wherein a typical first thickness of said third metal layer is at least 50% greater than a typical second thickness of said second metal layer.