CPC H01L 28/56 (2013.01) [H01L 21/02601 (2013.01); H01L 28/60 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/78391 (2014.09); H01L 29/78696 (2013.01); H10B 53/30 (2023.02)] | 20 Claims |
1. A memory device comprising a memory cell comprising:
a bottom electrode layer;
a high-k dielectric layer disposed on the bottom electrode layer;
a discontinuous seed structure comprising particles of a metal disposed on the high-k dielectric layer;
a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and
a top electrode layer disposed on the FE layer.
|