US 11,756,926 B2
Method for manufacturing a semiconductor package
Shun Sing Liao, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on May 24, 2022, as Appl. No. 17/752,796.
Application 17/752,796 is a continuation of application No. 16/894,630, filed on Jun. 5, 2020, granted, now 11,387,213.
Prior Publication US 2022/0285313 A1, Sep. 8, 2022
Int. Cl. H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01)
CPC H01L 24/97 (2013.01) [H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/49838 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 24/92 (2013.01); H01L 23/49827 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/98 (2013.01); H01L 2924/3511 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A substrate structure comprising:
a first lower structure disposed in a lower side rail; and
a second lower structure disposed in the lower side rail,
wherein a stress relieving ability of the first lower structure is greater than a stress relieving ability of the second lower structure, and a structural strength of the second lower structure is greater than a structural strength of the first lower structure, wherein in a top view, the second lower structure includes at least one row of segments, and the at least one row of segments is substantially parallel with an edge of the substrate structure, wherein the at least one row of segments includes a first segment and a second segment, and a width of the first segment is substantially equal to a width of the second segment, wherein a gap between the first segment and the second segment is greater than a width of a strip of the first lower structure.