	US 11,756,880 B2
	Interconnect structures
Cyprian Emeka Uzoh, San Jose, CA (US); Gaius Gillman Fountain, Jr., Youngsville, NC (US); and Jeremy Alfred Theil, Mountain View, CA (US)
Assigned to ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed on Sep. 27, 2021, as Appl. No. 17/486,633.
Application 17/486,633 is a continuation of application No. 16/657,696, filed on Oct. 18, 2019, granted, now 11,158,573.
Claims priority of provisional application 62/748,653, filed on Oct. 22, 2018.
Claims priority of provisional application 62/902,207, filed on Sep. 18, 2019.
Prior Publication US 2022/0013456 A1, Jan. 13, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01)

CPC H01L 23/5226 (2013.01) [H01L 23/298 (2013.01); H01L 23/3178 (2013.01); H01L 24/20 (2013.01)]

28 Claims

1. A method of manufacturing a device, the method comprising:

forming a cavity in a substrate extending at least partially through a thickness of the substrate from a surface of the substrate;

providing a conductive material in the cavity and over the surface of the substrate;

removing a portion of the conductive material thereby forming a recess on an upper surface of the conductive material;

providing a fill layer over the upper surface of the conductive material and the surface of the substrate;

removing at least a portion of the fill layer to expose at least a portion of the conductive material; and

forming a second cavity in the substrate extending at least partially though the thickness of the substrate from the surface of the substrate, a width of the second cavity being wider than a width of the cavity.