US 11,756,874 B2
Electronic device comprising a chip and at least one SMT electronic component
David Auchere, Meylan (FR); Claire Laporte, Grenoble (FR); Deborah Cogoni, Notre Dame de l'osier (FR); and Laurent Schwartz, La Buisse (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR); and STMicroelectronics (Alps) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR); and STMicroelectronics (Alps) SAS, Grenoble (FR)
Filed on Sep. 15, 2022, as Appl. No. 17/945,822.
Application 17/945,822 is a division of application No. 17/064,119, filed on Oct. 6, 2020, granted, now 11,482,487.
Claims priority of application No. 1911129 (FR), filed on Oct. 8, 2019.
Prior Publication US 2023/0015669 A1, Jan. 19, 2023
Int. Cl. H01L 23/50 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/50 (2013.01) [H01L 23/315 (2013.01); H01L 23/3128 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A process for producing an electronic device, comprising:
mounting an integrated circuit (IC) chip on top of a front face of a carrier substrate and connecting the IC chip to first electrical contacts of the front face of the carrier substrate;
forming an encapsulation block on top of the front face of the carrier substrate which embeds the IC chip;
making a through-void for positioning and confinement that extends through the encapsulation block, reaches the front face of the carrier substrate and exposes second electrical contacts of the front face of the carrier substrate;
placing a stack of electronic components in the through-void on top of the front face of the carrier substrate, wherein the through-void and the stack of electronic components are configured such that there is a clearance between flanks of the through-void and flanks of the stack of electronic components, and wherein an orientation of the stack of electronic components, parallel to the front face of the carrier substrate, is limited by at least two opposite flanks of the through-void;
dispensing solder material into the through-void such that the solder material penetrates into said clearance; and
hardening the solder material so that electrical connection terminals of each electronic component of the stack of electronic components are connected to the second electrical contacts of the front face of the carrier substrate by solder bumps or pads that are located in the through-void.