	US 11,756,836 B2
	3D device layout and method using advanced 3D isolation
H. Jim Fulford, Marianna, FL (US); Mark I. Gardner, Cedar Creek, TX (US); and Partha Mukhopadhyay, Oviedo, FL (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Sep. 21, 2021, as Appl. No. 17/480,380.
Claims priority of provisional application 63/188,033, filed on May 13, 2021.
Prior Publication US 2022/0367289 A1, Nov. 17, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 21/822 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01)

CPC H01L 21/823487 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823481 (2013.01); H01L 27/0688 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/41741 (2013.01)]

20 Claims

1. A method, comprising:

forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers;

forming vertically stacked lower and upper vertical channel structures that vertically extend through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer;

forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure;

forming a vertical opening in the layer stack; and

removing the sacrificial layer through the vertical opening to separate the lower and upper vertical channel structures.